1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and, more specifically to a semiconductor memory device including redundant memory cell arrays for repairing defects.
2. Description of the Background Art
Conventionally, semiconductor memory devices such as static random access memories (hereinafter referred to as "SRAMs") include redundancy circuits to improve production yield. If there is a defect in a manufactured semiconductor memory device, the semiconductor memory device is repaired by the function of the redundances circuit. Namely, in the conventional semiconductor memory device, a row or a column including a defective memory cell is functionally replaced by a predetermined spare row or a spare column. The present invention can be generally applied to semiconductor memory devices such as SRAMs and DRAMs. However, in the following description, an example in which this invention is applied to an SRAM will be described.
FIG. 23 is a block diagram of a conventional SRAM having a redundancy circuit. Referring to FIG. 23, the SRAM 100 includes a plurality of memory cell arrays 80 for storing data, a plurality of row decoders 82 responsive to a row address signal X for selecting a word line WL in the memory cell arrays 80, a plurality of column decoders 83 for selecting a column in the memory cell in response to a column address signal Y, a plurality of write driver circuits 84 and a plurality of sense amplifiers 85. The SRAM 100 further includes, as the redundancy circuit, a spare memory cell column 81, an address program circuit 86 for programming a defect address indicating the position of the defect, if any, and a plurality of I/O program circuits 87.
For one memory cell array 80, one row decoder 82, a column decoder 83, a write driver 84, a sense amplifier 85 and an I/O program circuit 87 are provided. In FIG. 23, the block on the left side is the same as the block on the right side except the address program circuit 86, and therefore the block on the left side will be mainly described in the following.
In operation, the row decoder 82 activates one word line WL in the memory cell array 80 in responds to an externally applied row address signal X. The column decoder 83 selects one column to be accessed in response to an externally applied column address signal Y. More specifically, the column decoder 83 selectively turns on a transmission gate TG1 connected to a column to be accessed, and electrically connects the bit line to a write driver circuit 84 or to the sense amplifier circuit 85. Therefore, in writing operation, an externally applied input data Di is written to a selected memory cell selected by the row decoder 82 and the column decoder 83. In reading operation, the data signal read from the memory cell selected by the row decoder 82 and the column decoder 83 is amplified by the sense amplifier 85, and the amplified signal is output as an output data Do.
If it is found that there is some defect in a certain memory column, the defective memory cell column is functionally replaced by the spare memory cell column 81 in the following manner. The defect address indicating the position of the defective memory column is programmed in an address program circuit 86 by selectively cutting a fuse (shown in FIG. 25). The address program circuit 86 includes a coincidence detecting circuit, not shown, and coincidence between an externally applied column address signal Y and the programmed address signal is detected. A coincidence detection signal CO is applied to the I/O program circuit 87.
A fuse in the I/O program circuit 87 (see FIG. 26) has been selectively cut in advance, and therefore the bit line in the spare memory cell column 81 is connected to the write driver circuit 84 and/or the sense amplifier 85 through a transmission gate circuit TG2. Consequently, if the column address signal Y coincides with the programmed address signal, the spare memory cell column 81 is accessed instead of the normal memory cell array 80. At this time, the transmission gate circuit TG1 is off.
Although two memory cell arrays 80 and the peripheral circuits 82, 83, . . . thereof are shown in FIG. 23 for convenience of description, generally a conventional SRAM includes a plurality of memory cell arrays and peripheral circuits thereof. Although one block of memory cell array and the peripheral circuit thereof only are shown in FIG. 23, there are a plurality, for example, 64, of blocks actually.
As is apparent from FIG. 23, one or two spare memory cell columns (or rows) are provided for every memory cell array 80, and therefore in the SRAM having a plurality (for example 64) of memory cell arrays includes 64 or 128 spare memory cell columns (or rows).
FIG. 24 is a block diagram of the address program circuit 86 shown in FIG. 23. The address program circuit 86 includes a plurality of fuse circuits 861 to 863 for programming the defect address, and AND gates 864 to 866 for detecting coincidence between the input address signal and the defect address. The fuse circuits 861 to 863 receive corresponding two of the plurality of bits of a column address signal. The number of the fuse circuits and the number of AND gates are changed corresponding to the number of bits of the address signal.
FIG. 25 is a schematic diagram showing the structure of the fuse circuit 861 shown in FIG. 24. The fuse circuit 861 shown in FIG. 25 includes AND gates 111 to 114 for pre-decoding column address signals Y0 and Y1 and fuses 115 and 116 for programming. By selectively cutting the two fuses 115 and/or 116, 2 bits of defect address signal can be programmed. When the fuses 115 and 116 are connected, the inverters 117 and 118 output voltages at high level, respectively. If the fuses 115 and 116 are cut, inverters 117 and 118 output voltages at low level. The AND gate 111 outputs a voltage at high level when column address signals Y0 and Y1 at high level are applied. The AND gate 112 outputs a voltage at a high level when a signal Y0 at high level and a signal Y1 at low level are applied.
The AND gate 113 outputs a high level voltage when the signal Y0 at the low level and the signal Y1 at the high level are applied. The AND gate 114 outputs a high level voltage when the signals Y0 and Y1 at low level are applied.
Therefore, when the fuses 115 and 116 are connected, for example, transmission gates 119 and 120 are turned on. In this case, when the column address signals Y0 and Y1 both at the high level are applied, the AND gate 111 outputs a signal C.sub.01 at the high level through the transmission gate 119 and 120. In other words, only when 2 bits of defect address programmed by "connection" of the fuses 115 and 116 coincide with the column addresses Y0 at the high level and Y1 at the high level, the fuse circuit 861 outputs the signal C.sub.01 at the high level. The signal C.sub.01 is applied to the AND gate 864 shown in FIG. 24.
As a result, the address program circuit 86 shown in FIG. 24 outputs an address coincidence detection signal COi at the high level only when the programmed defect address coincides with the externally applied column address.
FIG. 26 is a schematic diagram of the I/O program circuit 87 shown in FIG. 23. The I/O program circuit 87 shown in FIG. 26 includes a fuse circuit 136 which controls the transmission gate TG2 for input in advance, a transfer gate 137 connected between an input terminal 139 and an output terminal 140 and is opened/closed in response to an output signal from the fuse circuit 136, and an MOS transistor 138 connected between the output terminal 140 and the ground potential. The fuse circuit 136 includes, as does the address program circuit 86, a fuse 131, a capacitor 132, a high resistance 133, a P channel transistor 134 and a CMOS inverter 135.
In operation, when the fuse 131 is cut, current flows from the supply terminal through the capacitor 132 and the high resistance 133 to the input of the inverter 135, the input terminal of the inverter 135 attains "H" level and the output terminal of the inverter 135 attains "L" level. Therefore, the transfer gate 137 is turned on to pass the input data (output from the address program circuit 86). If the fuse 131 is not cut, the output terminal 140 is fixed to "L" level by means of the N channel transistor 138.
FIG. 27 is a schematic diagram showing the transmission gate circuits TG1 and TG2, the bit lines and the memory cells shown in FIG. 23. Referring to FIG. 27, the transmission gate circuit TG1 is connected between the bit line pair BLa, BLb in a normal memory cell array and a data line pair DLa and DLb. The transmission gate circuit TG2 is connected between a bit line pair RBLa and RBLb in a spare memory cell column and the data line pair DLa and DLb in a spare memory cell. FIG. 27 includes only one TG2, but actually there exist as many TG2s as the number of I/Os. The transmission gate circuit TG1 is turned on in response to a column selecting signal Y.sub.L at a high level applied from a column decoder (not shown), and therefore the bit line pair BLa and BLb is electrically connected to the data line pair DLa and DLb. Since the supply potential Vcc is applied to the gate of the NMOS transistor 89, the transistor 89 is turned on. However, since the transistor 89 has high channel resistance, the potential of the column selecting signal Y.sub.L is not influenced. Therefore, the column selecting signal Y.sub.L at the high level is correctly applied to the transmission gate circuit TG1 through a fuse 88.
If there is a defect in the memory cell MC1, the fuse 88 is cut. Therefore, the ground potential is applied to the transmission gate circuit TG1 through the transistor 89, and the transmission gate circuit TG1 is turned off. If a column address signal selecting the column where the memory cell MC1 exist is applied, a high level signal RY is applied to the transmission gate circuit TG2 through the I/O program circuit 87. Consequently, the transmission gate circuit TG2 is turned on, and as a result, the column including the memory cell MC1 is functionally replaced by the spare memory cell column 81.
As described above, the conventional semiconductor memory includes a plurality of memory cell arrays and one or two spare memory cell column provided corresponding to each memory cell array. Therefore, an SRAM having 64 memory cell arrays, for example, has a capability of repairing 64 or 128 defective memory cell columns. However, actually, the necessary capability of repairing is not so large. It is known from the experience that there is not so much defects in the semiconductor memory device. It is known that there may possibly be 10 defects at the most in the above mentioned SRAM. In other words, the conventional semiconductor memory has excessive spare memory columns or rows which are not necessary in actual use. Consequently, high degree of integration of the semiconductor memory has been prevented.
In addition, since the conventional spare memory column or row is provided per one memory array, it cannot be used for repairing a column or row in another memory cell array. In other words, if there are defects in three or more memory cell columns or rows, the defects cannot be repaired by using one or two spare memory columns or rows, and in such a case, repairing was impossible.
Further, as the pattern forming the memory cells becomes smaller and smaller, there is a high possibility that one defect bridges a plurality of columns, which leads to a problem that the semiconductor memory device itself cannot be repaired even if one column of memory cells can be repaired.